1. Field of the Invention
The present invention relates to an analog-to-digital converter (referred to as an AD converter hereinafter) and a time-to-digital converter (referred to as a TD converter hereinafter), which use operation in the time domain using neither any operational amplifier nor any switched capacitor estimated to be unsuitable for process scale shrinkage.
2. Description of the Related Art
For further developments of information communication apparatuses, it is absolutely indispensable to develop LSIs of less consumption power, higher performance and lower cost than in the conventional case. The performances of LSIs have been improved up to now in accordance with scale shrinkage of semiconductor manufacturing processes. The transistor count per chip has increased every year by virtue of scale shrinkage, and this makes it possible to actualize LSIs of higher performances.
However, in analog circuits such as operational amplifiers and switched capacitors, scale shrinkage has become more difficult due to the problems of dynamic range and non-linearity. In particular, under the environment of low supply voltages in advanced processes, the dynamic range is narrowed and the linearity is deteriorated, causing difficulties in securing gains.
Therefore, in a mixed-signal chip where a digital circuit and an analog circuit are mixed, the analog circuit block is a barrier to hinder the power consumption reduction and cost reduction. Moreover, upon configuring a mixed-signal chip, the digital circuit discriminates between “1” and “0” depending on whether the signal voltage is higher or lower than a reference value, and therefore, a configuration robust to variations in the device characteristics is possible. On the contrary to it, the analog circuit purely processes the signal waveform as it is, there is such a problem that degradation in the signal processing accuracy is incurred by variations in the device characteristics. The transistor size shrinks as the scale shrinkage of semiconductor processes progresses, and reductions in the power voltage progresses in accordance with the same situation. The variations in the device characteristics of individual transistors become large, and the problem of disadvantageously giving superfluous influences to the signal to be processed has become increased.
Various disincentive factors such as a reduction in the gain of the operational amplifier, a deterioration in the linearity, and a degradation in the SN ratio due to a reduction in the signal voltage amplitude caused by the lowered power voltage occur in accordance with the scale shrinkage of semiconductor processes, and it is getting more difficult to design the analog circuit part that configures the mixed-signal chip.
Under such a situation, regarding AD converters that are important components in mixed-signal chips to be applied to wireless communications, data sensing and the like, the AD converters, which have been conventionally difficult in being adapted to scale shrinkage because of the configuration employing operational amplifiers and accompanying capacitors, are driven toward operational amplifier-free capacitor-free configurations as a trend in recent years.
On the other hand, a TD converter (referred to as a TDC) for converting a delay value into a digital value has been known, and a Gated-Ring-Oscillator TDC (hereinafter, referred to as a “GRO TDC”) as shown in FIG. 1 has been known as a TD converter that utilizes a ring oscillator.
In the case of the GRO TDC, a pulse width that temporally changes is inputted (Tin) to the GRO, and the width of the input pulse is quantized by counting the output oscillation waveform (GROout) of the GRO within the width of the input pulse, allowing the discretized digital data (Dout) to be obtained in a form of counted value.
That is, as shown in the operation concept diagram of the GRO TDC of FIG. 2, oscillation output (GROout) of the GRO is made while the input pulse (Tin) to the GRO is raised, and the value (Dout) obtained by counting the oscillation contains a quantization error (QN) taken out of the oscillation waveform of the GRO.
It has been known that the GRO TDC has a noise shaping characteristic of first-order Δ-Σ modulation (See the Non-Patent Document 1), whereas the conventional disclosure remains demonstrating a circuit configuration that has a first-order noise shaping function.
A prior art document related to the present invention is as follows:
Non-Patent Document 1: Matthew Z Straayer, et al., “A Multi-Path Gated Ring Oscillator TDC With First-Order Noise Shaping”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. 44, No. 4, April 2009.
It is difficult for the aforementioned GRO TDC, which utilizes the conventional ring oscillator, to improve the performance since it can obtain only the first-order noise shaping. Moreover, a configuration to obtain higher-order noise shaping in the voltage domain in combination with operational amplifiers in a manner similar to that of the conventional case has such a problem that it is unsuitable for a broad area, a high power consumption, and minute processes due to problems such as securing of operational amplifier performance and the like.